The present invention relates to logic circuit design technology, and more particularly, to a method for optimizing the number of logic gates in a logic gate array.
An established method of logic circuit design is to manually design the desired logic circuit. Given desired input to output logic relationships or functions, logic schematics are designed. These relationships expressed as boolean algebraic functions and the resulting logic circuits are typically simplified using conventional algebraic simplification methods, Karnaugh maps, truth tables and the like.
Computers are also currently used to design an integrated circuit device corresponding to a finalized logic function. In this process, the computer executes a program to transform a high level description of a digital logic circuit into an integrated circuit implementation of that design. The synthesis techniques used in the computer programs typically implement a set of logic functions treating common terms in the relationships independently. This causes redundant implementation of logic functions having common terms and results in redundant logic gates in the final circuit. These computer techniques do not attempt to find and group common inputs coupled to basic or first level logic gates such as AND or OR gates. Logic circuits designed by conventional computer programs may also use wide logic gates (gates having more than four inputs). The use of wide gates can degrade signal strength and switching speed of a gate array. Such an approach requires increased repowering of the logic gate array. For these and similar reasons, logic circuits designed by conventional computer programs are not optimally fast or efficient.
Accordingly, it is an objective of the present invention to provide an improved method of logic gate reduction in a logic gate array. Another objective of the present invention is to simplify the design of digital circuits. A further objective of the present invention is to provide a method for designing logic gate arrays having increased operating speed, that use less power, and that are produced at reduced cost.